The present invention relates generally to the field of semiconductor device fabrication and, more particularly, to methods for improving metal-to-metal contact in vias by decreasing and/or repairing damage to metal layers during formation of damascene structures in semiconductor devices.
The integration of a large number of components on a single integrated circuit (IC) chip requires complex interconnects. Ideally, the interconnect structures should be fabricated with minimal signal delay and optimal packing density. The reliability and performance of integrated circuits may be affected by the quality of their interconnect structures. Advanced multiple metallization layers have been used to accommodate higher packing densities as devices shrink below sub-0.25 micron design rules. One such metallization scheme is a dual damascene structure formed by a dual damascene process. The dual damascene process is a sequential mask/etch process to form a two-level structure, such as a via connected to a metal line situated above the via.
In contrast to a single damascene process, the via and the trench are simultaneously filled with metal. Thus, compared to the single damascene process, the dual damascene process offers the advantage of process simplification and low manufacturing cost.
To improve the performance, reliability and density of the interconnects, the microelectronics industry has recently begun migrating away from the use of aluminum (Al) and/or its alloys for the interconnects. As such, advanced dual damascene processes have begun using copper (Cu) as the material of choice because copper has high conductivity, extremely low resistivity (about 1.7 μΩcm) and good resistance to electromigration. One difficulty encountered with copper is that copper-to-copper connections between the first level interconnect metal layer and a copper via-filling plug are subject to reliability problems due to chemical and physical damage to the first level interconnect metal layer during formation of the dual damascene structure.
FIGS. 1A-1C illustrate a sequence of fabrication steps for a known dual damascene process as applied to interconnect formation. As shown in FIG. 1A, the process begins with the deposition of a first insulating layer 140 over a first level interconnect metal layer 120, which in turn is formed over or within a semiconductor substrate 100. A second insulating layer 160 is next formed over the first insulating layer 140. Etch stop layers 150, 150′ are typically formed between the first and second insulating layers 140, 160 and between the first insulating layer 140 and the first level interconnect metal layer 120. The second insulating layer 160 is patterned by photolithography with a first mask (not shown) to form a trench 170 corresponding to a metal line of a second level interconnect. The etch stop layer 150 prevents the upper level trench 170 from being etched through to the first insulating layer 140.
As illustrated in FIG. 1B, a second masking step followed by an etch step is applied to form a via 180 through the etch stop layer 150 and the first insulating layer 140. The second etch stop layer or barrier layer 150′ is formed between the first level interconnect metal layer 120 and the first insulating layer 140 during the formation of the dual damascene structure 125. Thus, a further step is required to open barrier layer 150′ and expose the underlying first level interconnect metal layer 120. After the etching is completed, both the trench 170 and the via 180 are filled with metal 122 (also referred to as via-filling plug 122), which is typically copper (Cu), to form a damascene structure 125, as illustrated in FIG. 1C.
FIGS. 1D-1F depict one problematic result that arises with known damascene processing techniques. Among other contaminants, copper oxide 121 is formed in the first level interconnect metal layer 120 by the oxidizing etchants conventionally used to open barrier layer 150′, as shown in FIG. 1D. Such damage to first level interconnect metal layer 120 often further includes undercutting (i.e., removal of material from first level interconnect metal layer 120 under barrier layer 150′) of the first level interconnect metal layer 120 near the edges of barrier layer 150′ (see also FIG. 1F). Copper oxide and other contaminants must be removed prior to formation of the via-filling plug 122, which is typically accomplished with a wet clean process. As shown in FIGS. 1E-1F, removal of copper oxide 121 in such a wet clean process sometimes causes voids 127 to occur during formation of the via-filling plug 122. Such voids 127 compromise the reliability of the electrical connection between plug 122 and the first level interconnect metal layer 120 and are particularly likely to occur near or under the edges of the barrier layer 150′, as shown in FIGS. 1E-1F.
FIG. 1F is a detail view of region 190 shown in FIG. 1E. FIG. 1F shows the aforementioned undercutting of first level interconnect metal layer 120 near the edges of barrier layer 150′, as well as voids 127 that can form due, at least in part, to such undercutting.
In the past, hydrogen plasmas have been used after the wet clean process described above. However, such an approach is disadvantageous because the wet clean process selectively removes copper oxides 121 from first level interconnect metal layer 120, thus giving rise to greater potential for incidence of voids 127 and other anomalies in subsequently formed metal-to-metal contacts, e.g., between via-filling plug 125 and first level interconnect metal layer 120. The present invention advantageously overcomes this problem by at least partly reducing copper oxide to copper before the wet clean process, thus reducing the amount of copper material removed by the wet clean process and concomitantly improving the reliability of subsequently formed metallic connections.
As mentioned above, copper interconnect is the most promising metallization scheme for the future generation high-speed ULSI, primarily because of lower electrical resistivity (1.7 vs. 2.3 μΩcm) and electro/stress-migration resistance than the conventional aluminum-based materials. However, copper metallization suffers from disadvantages, including those described above. As a result, in order to adopt copper interconnects for ULSI, suitable methods for improving the reliability of copper-to-copper contact in vias are needed.
As mentioned above, of the several schemes proposed for fabricating copper interconnects, the most promising method appears to be the dual damascene process shown in FIGS. 1A-1C. Using this method, the trenches for conductors and holes for vias are patterned in blanket dielectrics, and then the desired metal is deposited into the trenches and holes in one step. Chemical mechanical planarization (CMP) is conventionally used to remove the unwanted surface metal extending over the uppermost dielectric, while leaving the desired metal in the trenches and vias. This leaves a planarized surface for subsequent metallization to build multilevel interconnect structures. Unfortunately, this technology not only uses a large amount of expensive consumables for the CMP process and the associated waste disposal problem but also is very wasteful of copper. Typically, the conductors and vias in a given metallization level occupy only a small proportion of the deposited copper, while the bulk of the copper is removed by CMP, rendering the technology very expensive. There is thus a strong economic incentive to minimize waste wherever possible, and losses that can occur due to defective metal-to-metal contact in vias are especially onerous because they occur and/or are discovered only after substantial fabrication is complete.
The ordinarily skilled artisan will readily appreciate that a number of processes are known for forming dual damascene structures. For instance, trenches may be etched through the upper insulating layer, after which a further mask may be employed to etch the contact vias, or the etch continues through a previously defined, buried hard mask (the so-called “trench first” approach). Alternatively, vias may first be etched through the upper and lower insulating layers, after which the via in the upper insulating layer may be widened to form a trench (the so-called “via first” approach). The “via first” dual damascene approach has been widely adopted for small geometry devices.
Due to the disadvantageous results (as depicted in FIGS. 1E-1F) that can arise in conventional damascene techniques, great care is taken to minimize physical and chemical damage to the first level interconnect metal (copper) layer 120. Nevertheless, known damascene techniques still frequently result in formation of voids 127, which are undesirably detrimental to the integrity of the electrical connection between the first level interconnect metal layer 120 and the conductive via-filling plug 122.
It can thus be seen that a need exists for improved dual damascene processing techniques that provide improved electrical connections in vias.